1. Field of the Invention
This invention relates to a method of detecting and reporting a condition associated with a substrate having an integrated circuit chip mounted thereto.
2. Description of Prior Art
Currently, the condition of such substrates is assessed only once, at the time that the substrate and chip have been joined together and are being readied for shipment as a complete electronic package. If the package then meets requirements, no further monitoring is done of its condition. Clearly, it would be desirable to be warned of any deterioration of its condition after the electronic package is put into service. See, for example S. L. Buchwalter et al., “Effect of Mechanical Stress and Moisture On Packaging Interfaces”, IBM Journal of Research and Development, Vol. 49, July 2005 which outlines some of the reliability problems faced with electronic packages, especially where two surfaces meet.
Moreover, after such substrate-chip package is put into service in a computer product, it then undergoes stresses that have not been experienced during its production. As will be understood it would be desirable to monitor the effects of such stresses on the condition of the electronic package during its operation.
As is well known, such substrates may comprise various materials, such as organic and in organic. See, E. D. Blackshear et al., “The evolution of Build-Up Package Technology and Its Design Challenges”, IBM Journal of Research and Development, Vol. 49, July 2005 for a paper on organic packages, Examples of inorganic include ceramic such as glass-ceramic and Alumina. Electronic packages are assembled from substrates, integrated circuit chips, passive components and a printed circuit board (PCB). They are stress tested to predict field life. The actual packages tested are specially designed and built to be tested under specific stress conditions. An example of a test would be where a package is powered up and powered down until it fails. The tools and testers designed are custom built to accommodate these specially designed test packages. These test packages are non-production hardware designed for the sole purpose of the stress tests. Data gathered from these tests are used by a statistical model that predicts time to failure. Essentially these models and data are used to predict field life. See, for example, Microelectronic Packaging Handbook, Semiconductor Packaging Part II, second edition, edited by Rao R. Tummala, Copyright 1997, Kluwer Academic Publisher, pages II-35-II-36.
The flaws in this methodology are, a) the mechanism of failure in the field may not be represented by the stress test. Sometimes the mechanism the test is designed for does not occur in the field, b) the sample sizes required to accurately predict the life time in the field are not large enough due to the expense associated with conducting the tests, c) certain test have been around so long and are so firmly established, they must be run as defined even if more recent knowledge renders them obsolete, and d) it is difficult in many of the stress test to determine exactly when the failure occurred.
The key flaw is actual production hardware is almost never stressed in some of the key stress tests. The way in which production packages are built, the shipping environment they are exposed to, and the process chemicals they are exposed to can make production hardware different than specialized electronic packaging for stressing.
Clearly if one could assess the life of actual production packages in the field it would better to measure field life to measure with the one time specialized tests currently employed.
Many electronic packaging applications are changing to use organic substrates, also referred to as an organic laminate package or simply an organic chip carrier. Organic substrates have high electrical conductivity, low inductance connections to reduce switching noise, and a low dielectric constant insulator to better match printed circuit board impedance. Most importantly the organic substrate has lower cost.
Some of the disadvantages of organic substrates are higher coefficient of thermal expansion (CTE) compared to the silicon chip mounted on the organic substrate and sensitivity to atmospheric humidity. Organic substrates have a CTE of 18 ppm which is much higher than that of Silicon (CTE˜3 ppm). The CTE mismatch leads to higher dimensional distortion, to more stress on the chip, and to more stress on solder joint interconnections of the semiconductor chip to the organic substrate. Undesirable strain resulting from the stress can reduce the life of the substrate. With the introduction of lead free solder, the substrate is exposed to even higher reflow temperature of about 220° C. compared to reflow temperatures of lead/tin solder interconnections. This is a problem because physical properties of the material deteriorate above the glass transition temperature (Tg) of the organic material portion of the organic substrate. Above Tg the organic material may warp. The critical temperature for warpage may be between 120-180° C. for these organic materials. Even below Tg, the combination of mechanical stress and humidity work together to weaken the adhesive interface.
The organic substrate itself is quite complex. It may be composed of over 10 copper layers, laminated with layers of organic resin filled glass fiber. The copper layers are etched into several thousand electrically conducting lines in many different orientations. The resin layers may contain a non-uniform distribution of plated thru holes (PTH). This anisotropic metal loading on the layers can be a contributor to the degradation of field like when exposed to the aforesaid stresses. With constant introduction of new materials, new manufacturing processes, and diverse operating conditions, the reliability data gathered by a one time reliability assessment with non-product test vehicle substrates is unable to predict failure conditions occurring in real time. Having a more predictive assessment of field life would be highly desirable. Current methods of assessment are not doing a good job predicting when a production organic electronic package will fail.
Moreover, ceramic substrates also suffer from similar shortcomings that could be remedied by in-situ reliability assessment. There is a TCE mismatch between the printed wiring board material, also known as the printed circuit board (PCB), connected to the ceramic substrate and the ceramic substrate itself. As I/O counts increase (number of solder connections and distance of the connection furthest from the center) the distance from neutral point drives stress in the outer solder ball connections during thermal and power cycling in the field. The key solution to this problem is to be able to predict the actual life time in the field for individuals of a given product design and production lot under actual field conditions.